Level shifting circuit and method
US10778227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Sep 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifting circuit includes a shift circuit configured to output first and second voltage signals according to level signals, and an input circuit configured to carry out inversion and delay operations on input level signals to obtain first, second, third, and fourth level signals. Rising edge of the first level signal is earlier than falling edge of the second level signal by a first preset time. Falling edge of first level signal is later than rising edge of the second level signal by a second preset time; the third level signal is obtain by delaying the first level signal by a third preset time, and the fourth level signal is obtain by delaying the second level signal by a fourth preset time; the first preset time is longer than the third preset time, and the second preset time is longer than the fourth preset time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.