Clock dividing frequency circuit, control circuit and power management integrated circuit
US10778231B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2017 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Dec 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K4/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock dividing frequency circuit can include: a controlled current source configured to generate a driving current that varies with a dividing frequency control signal; a ramp signal generating circuit configured to generate a ramp signal having a slope that varies according to the driving current, where the ramp signal is reset according to pulses of a dividing frequency clock signal; and a dividing frequency pulse generating circuit configured to generate the dividing frequency clock signal by a dividing frequency operation according to the ramp signal and a system clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.