Clock generation circuit and clock signal generation method
US10778234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Nov 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generation circuit and a clock signal generation method are disclosed. In the method, a direct current bias circuit in a first clock source superimposes a first direct current voltage on a first clock signal output by a first oscillation circuit, to generate a second clock signal; and a logical operation is performed on the second clock signal and a third clock signal that is generated by a second clock source, to generate a fourth clock signal. The fourth clock signal is used as a signal output by a clock generation circuit. In the method, when the first oscillation circuit cannot normally work, the clock generation circuit can still output a correct clock signal. This avoids clock signal interruption when switching is performed from the first clock source to the second clock source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.