Delay-based residue stage
US10778243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2020 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Apr 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input. The analog-to-digital converter further includes a digital block having an input connected to the sign signal output of the delay comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.