Method and apparatus of a fully-pipelined layered LDPC decoder
US10778250B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Feb 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/116
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.