Method and apparatus for encoding quasi-cyclic low-density parity check codes
US10778251B2 · kind B2 · utility
3Cited by
6References
25Claims
0Family size
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Key dates
| Filing date | Aug 2, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Aug 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for encoding low-density parity check codes uses parity check matrices composed of circulant blocks. The apparatus operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardware implementation, and high encoding throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.