Patent · US Active

Deeply-pipelined high-throughput LDPC decoder architecture

US10778371B2 · kind B2 · utility

2Cited by

7References

30Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Vincent Loncke · Piscataway, US
Girish Varatkar · Fryeburg, US
Thomas Richardson · South Orange, US
Yi Cao · Parsippany, US

Key dates

Filing date	Sep 22, 2017
Grant date	Sep 15, 2020
Priority date	—
Expiry date	May 30, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1443
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs. Accordingly, aspects of the present disclosure provide techniques for reducing delays in a processing pipeline by, in some cases, relaxing a dependency between updating bit log likelihood ratios (LLRs) and computing a posteriori LLRs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.