Synthesized clock synchronization between networks devices
US10778406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Dec 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.