Local instruction ordering based on memory domains
US10782896B2 · kind B2 · utility
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36Claims
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Key dates
| Filing date | Jan 4, 2019 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | May 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.