Gate driver and flat panel display device including the same
US10783820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2018 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Oct 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are a gate driver capable of implementing a narrow bezel by deleting dummy gate-in-panels (GIPs) and a flat panel display device including the same. The gate driver includes gate-in-panels (GIPs) equal in number to a plurality of gate lines in order to sequentially supply scan pulses to the plurality of gate lines. A k-th GIP is enabled by a carry pulse from a GIP of a (k−a)-th stage and is disabled by a carry pulse output from a GIP of a (k+b)-th stage (a and b are natural numbers), first a GIPs are enabled by a gate start signal output from a timing controller, and last b GIPs are disabled by a reset signal output from the timing controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.