Slit stress modulation in semiconductor substrates
US10784144B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2018 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Feb 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.