Multi-wafer stacking structure and fabrication method thereof
US10784163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2018 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Dec 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06544
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-wafer stacking structure and a fabrication method thereof are disclosed. A first dielectric layer and a second dielectric layer are bonded to each other, a first interconnection layer is electrically connected with a second metal layer and a first metal layer via a first opening; a third dielectric layer and an insulating layer are bonded to each other, and a second interconnection layer is electrically connected with a third metal layer and the first interconnection layer via a second opening. Reservation of a pressure welding lead space among wafers is not needed, a silicon substrate is omitted, multi-wafer stacking thickness is reduced while interconnection of multiple pieces of wafers is realized, and therefore, the overall thickness of the device after multi-wafer stacking and packaging is reduced, packaging density is increased, and the requirement of thinning of the semiconductor products is met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.