Method of manufacturing array substrate and array substrate
US10784290B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2019 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Apr 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/451
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an array substrate and an array substrate are provided. The method of manufacturing the array substrate includes forming a first metal layer on a substrate, wherein the first metal layer includes a plurality of first metal lines and a plurality of intermittent second metal lines, forming an interlayer dielectric insulating layer on the substrate and the first metal layer, and forming an intermittent data line on the interlayer dielectric insulating layer and the first metal layer, wherein the intermittent data line contacts the two ends of each of the intermittent second metal lines through the via holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.