Castellated superjunction transistors
US10784341B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2019 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Jan 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.