Segmented digital to analog converter
US10784886B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2020 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Feb 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/80
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.