High throughput hardware unit providing efficient lossless data compression in convolution neural networks
US10784892B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2019 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Jul 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1117
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first memory interface circuit and a decompression circuit coupled to the first memory interface circuit. The decompression circuit may be configured to (i) receive a reduced size representation of a coding block of data comprising a first bit map, a second bit map, and zero or more non-zero values from an external memory via the first memory interface circuit, (ii) losslessly restore the coding block of data from the reduced size representation of the coding block using the first bit map, the second bit map, and the zero or more non-zero values, and (iii) transfer the restored coding block of data to a processing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.