High performance data redundancy and fault tolerance
US10784896B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2019 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Mar 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/616
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One embodiment provides a system that facilitates numerical operation-based erasure coding. During operation, the system determines the bit-width of processing capability of the computing system. The system then determines, based on the bit-width, a number of bits for representing a respective data element from a data stream and a number of data elements based on a number of a dimension of a generator matrix of erasure encoding. The system then obtains the number of data elements from the data stream and converts a respective obtained data element to a corresponding numerical representation. Here, a respective obtained data element is represented by the determined number of bits. The system then generates a code word, which comprises a plurality of coded fragments, of erasure encoding from the numerical representations based on the generator matrix of the erasure encoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.