Technologies for scalable translation caching for binary translation systems
US10789056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2016 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Sep 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/61
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies for binary translation include a computing device that allocates a translation cache shared by all threads associated with a corresponding execution domain. The computing device assigns a thread to an execution domain, translates original binary code of the thread to generate translated binary code, and installs the translated binary code into the corresponding translation cache for execution. The computing device may allocate a global region cache, generate region metadata associated with the original binary code of a thread, and store the region metadata in the global region cache. The original binary code may be translated using the region metadata. The computing device may allocate a global prototype cache, translate the original binary code of a thread to generate prototype code, and install the prototype code in the global prototype cache. The prototype code may be a non-executable version of the translated binary code. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.