Methods and apparatus for correcting out-of-order data transactions between processors
US10789110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2018 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Nov 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/329
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.