Fault tolerant charge parity qubit
US10789123B2 · kind B2 · utility
1Cited by
2References
19Claims
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Key dates
| Filing date | Apr 18, 2019 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Apr 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N60/805
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A quantum computer architecture employs logical qubits that are constructed from a concatenation of doubly periodic Josephson junction circuits. The series concatenation of the doubly periodic Josephson junction circuits provides exponential robustness against local noise. It is possible to perform discrete Clifford group rotations and entangling operations on the logical qubits without leaving the protected state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.