Network traffic rate limiting in computing systems
US10789199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2018 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Apr 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/161
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a computing device includes a field programmable gate array (“FPGA”) that includes an inbound processing path and outbound processing path in opposite processing directions. The inbound processing path can forward a packet received from the computer network to a buffer on the FPGA instead of the NIC. The outbound processing path includes an outbound multiplexer having a rate limiter circuit that only forwards the received packet from the buffer back to the computer network when a virtual port corresponding to the packet has sufficient transmission allowance. The outbound multiplexer can also periodically increment the transmission allowance based on a target bandwidth for the virtual port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.