Computer-implemented method of performing parallelized electronic-system level simulations
US10789397B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2016 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Jun 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing Electronic System Level simulation using a multi-core computing system comprises the steps of: A) Running a Discrete Event Simulation kernel on a core of the multi-core computing system, within a dedicated OS-kernel-level thread; B) Using the Discrete Event Simulation kernel for generating a plurality of OS-kernel-level threads, each associated to a respective core, and for distributing concurrent processes of the simulation among them; C) Carrying out parallel evaluation of the concurrent processes within the corresponding threads using respective cores; and then D) Using the Discrete Event Simulation kernel for processing event notifications, updating a simulation time and scheduling next processes to be evaluated; steps C) and D) being carried out iteratively until the end of the simulation. A computer program product including a hardware description Application Program Interface and a Discrete Event Simulation kernel adapted for carrying out such a method is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.