System, method, and computer program product for generating a formal verification model
US10789404B1 · kind B1 · utility
1Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jun 6, 2019 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Jun 6, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a specification model associated with an electronic design and generating, using a parser, an intermediate representation based upon, at least in part, the specification model. Embodiments may also include applying a machine generated semantic preserving program transformation to the intermediate representation to create a semantically transformed specification model and synthesizing the semantically transformed specification model to generate a formal verification model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.