Patent · US Active

Analog design tool having a cell set, and related methods

US10789407B1 · kind B1 · utility

0Cited by

23References

12Claims

0Family size

Assignee

Silicon Technologies, Inc. · US

Inventors

Kent F. Smith · Jacksonville, US
Thomas L. Wolf · Webster, US
Tracy Johancsik · Murray, US
Thomas Wolf · Barsinghausen, DE
Kyler C. Fillerup · Orem, US

Key dates

Filing date	Mar 29, 2017
Grant date	Sep 29, 2020
Priority date	—
Expiry date	Nov 17, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/18
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for designing a semiconductor integrated circuit is disclosed, including generating a physical layout from a schematic layout of the analog integrated circuit. The method comprises retrieving, with a processor, pre-defined cells having physical layout information for a specific process stored in a memory device responsive to the schematic layout being created by an analog circuit designer using an analog design tool, building the physical layout by connecting the retrieved pre-defined cells according to the schematic layout, and storing the physical layout in the memory device. Related systems and computer-readable media are also described herein.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.