Overlay structure and method of fabricating the same
US10790205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2019 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Jan 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method includes: forming overlay structures at scribe lines of a wafer, each side of a die region of the wafer is disposed with at least one of the overlay structures, each of the overlay structures comprises at least one feature and at least one recess disposed above the feature, the feature and the recess are respectively disposed at a first and second layers of the wafer, the recess exposes a portion of the feature vertically aligned with the recess; acquiring an image of the overlay structures; measuring a first dimension and a second dimension of a first portion and a second portion of the recess, respectively; determining an overlay between the first and second layers of an edge region of the wafer based on an average of differences between the first and second dimensions; and modifying a subsequent lithography step to compensate for the overlay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.