Patent · US Active

Semiconductor device with interconnect structure and fabrication method thereof

US10790227B2 · kind B2 · utility

0Cited by
2References
20Claims
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Key dates

Filing dateMar 5, 2019
Grant dateSep 29, 2020
Priority date
Expiry dateMar 5, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L23/53228
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a first dielectric layer having a first region and a second regions at each of two sides of the first region on the semiconductor substrate; forming a first opening in the first region of the first dielectric layer and a second opening in each of the second regions of the first dielectric layer; forming a first interconnect member in the first opening; forming a second interconnect member with a top surface lower than a top surface of the first dielectric layer in each of the second openings; forming a second dielectric layer having a third opening with a bottom exposing a top surface of the first interconnect member on surfaces of the first interconnect member, second interconnect members and the first dielectric layer; and forming an interconnect structure in the third opening.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.