SCRs with checker board layouts

US10790274B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Yu-Ti Su · Tainan, TW
• Wun-Jie Lin · Hsinchu, TW
• Han-Jen Yang · Taipei, TW
• Shui-Ming Cheng · Baoshan, TW
• Ming-Hsiang Song · Baoshan, TW

Key dates

• Filing date: Oct 19, 2017
• Grant date: Sep 29, 2020
• Expiry date: Jun 13, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/713

Abstract

An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.