Semiconductor device and method for manufacturing the same
US10790388B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Jul 16, 2018 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Nov 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/661
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.