Auto zero offset current mitigation at an integrator input
US10790791B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2018 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Nov 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45514
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A feedback stage for an integrator circuit is provided. The integrator receives a first input current and a second input current that include respective measurement current components and an offset current component. The integrator integrates the first input current and the second input current and generates a first output voltage and a second output voltage. The feedback stage including a transconductance amplifier detects a difference between the first output voltage and the second output voltage and sinks or sources a first output current and a second output current based on the difference between the first output voltage and the second output voltage. The first output current is additively combined with the first input current and the second output current is additively combined with the second input current to mitigate the offset current component at an input of the integrator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.