Signal amplitude aware dithering method for enhancing small signal linearity in an analog-to-digital converter
US10790850B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2019 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Jun 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/424
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) and a method are disclosed. The ADC includes dithering circuitry. The dithering circuitry includes a signal level detector, a dither amplitude controller, a random code generator, and a dither digital-to-analog converter (DAC). The signal level detector receives the analog input signal and provides amplitude level information associated with the analog input signal. The dither amplitude controller receives the amplitude level information from the signal level detector, and provides a control signal. The dither amplitude controller varies the control signal based on the amplitude level information. The dither DAC receives the control signal from the dither amplitude controller and a pseudo-noise (PN) signal from the random code generator, and provides the dither signal based on the control signal. The dither signal varies based on an amplitude level of the analog input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.