Duty-cycle control for power-level adjustment in switch-mode power amplifiers
US10794971B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2018 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Mar 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R33/3628
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An approach for accurately setting a duty cycle of PA switching waveforms uses an all-digital PVT sensor circuit. In various embodiments, the all-digital PVT sensor circuit measures a pulse width of a periodic reference signal using digital delay line, and subsequently, implements an off-chip digital calculation to program the digital delay line to delay this periodic reference signal so that, when the delayed periodic reference signal is combined with the original (undelayed) reference via a logical AND operation, the resulting signal conforms to a desired duty cycle. In one implementation, the PA is a class-D PA, which may have a single-ended configuration or a differential configuration having two single-ended structures operating in opposite phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.