Vector friendly instruction format and execution thereof
US10795680B2 · kind B2 · utility
Assignee
Inventors
- Robert Valentine
- Jesus Corbal San Adrian
- Roger Espasa Sans
- Robert Dale Cavin
- Bret L. Toll
- Santiago Galan Duran
- Jeffrey G. Wiedemeier
- Sridhar Samudrala
- Milind B. Girkar
- Edward T. Grochowski
- Jonathan C. Hall
- Dennis R. Bradford
- Elmoustapha Ould-Ahmed-Vall
- James C. Abel
- Mark J. Charney
- Seth Abraham
- Suleyman Sair
- Andrew T. Forsyth
- Lisa K. Wu
- Charles R. Yount
Key dates
| Filing date | Feb 28, 2019 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Apr 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.