Instruction length decoding
US10795681B2 · kind B2 · utility
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4References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Dec 23, 2014 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Jun 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a binary translator an a decoder. The binary translator includes logic to analyze a stream of atomic instructions, identify words by boundary bits in the atomic instructions, generate a mask to identify the words, and load the mask and the plurality of words into an instruction cache line. The words include atomic instructions. At least one word includes more than one atomic instruction. The decoder includes logic to apply the mask to identify a first word from the instruction cache line and decode the first word based upon the applied mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.