Method and logic for maintaining performance counters with dynamic frequencies
US10795684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2016 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Jun 6, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a front end including circuitry to decode an instruction from an instruction stream and a core including circuitry to process the instruction. The core includes an execution pipeline, a dynamic core frequency logic unit, and a counter compensation logic unit. The execution pipeline includes circuitry to execute the instruction. The dynamic core frequency logic unit includes circuitry to squash a clock of the core to reduce a core frequency. The clock may not be visible to software. The counter compensation logic unit includes circuitry to adjust a performance counter increment associated with a performance counter based on at least the dynamic core frequency logic unit circuitry to squash a clock of the core to reduce a core frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.