Fault tolerant clock monitor system
US10795783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2018 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Apr 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.