Patent · US Active

Method and apparatus for maintaining data coherence in a non-uniform compute device

US10795815B2 · kind B2 · utility

2Cited by

7References

15Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Jonathan Curtis Beard · Austin, US
Wendy Arnott Elsasser · Austin, US
Stephan Diestelhorst · Dresden, DE

Key dates

Filing date	May 27, 2016
Grant date	Oct 6, 2020
Priority date	—
Expiry date	Apr 14, 2038

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.