Multi-processor system with configurable cache sub-domains and cross-die memory coherency
US10795819B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2019 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Jun 26, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments relate to a system with configurable cache sub-domains and cross-die memory coherency. In one example, a system includes R racks, each rack housing N nodes, each node incorporating D dies, each die containing C cores and a die shadow tag, each core including P pipelines and a core shadow tag, each pipelines associated with a data cache and data cache tags and being either non-coherent or coherent and one of X coherency domains, wherein each pipeline, when needing to read a cache line, issues a read request to its associated data cache, then, if need be, issues a read request to its associated core-level cache, then, if need be, issues a read request to its associated die-level cache, then, if need be, issues a no-cache remote read request to a target die being mapped to hold the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.