Partial selection-based model extraction from circuit design layout
US10796042B1 · kind B1 · utility
1Cited by
1References
20Claims
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Key dates
| Filing date | Apr 22, 2019 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Apr 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide for partial selection-based (e.g., cut-based) model extraction from a layout of a circuit design, which can be used to generate a schematic extracted view for the circuit design and to back annotate a schematic of the circuit design. For some embodiments, the selection comprises a cut of a layout of a circuit design, where the cut may be defined (e.g., inputted) by a user through a graphical user interface that is presenting the layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.