EDA CAA with learning phase

US10796067B1 · kind B1 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Jonathan R. Fales · South Burlington, US
• Frank E. Gennari · Berkeley, US
• Jeffrey E. Nelson · Kinston, US
• Jeffrey Lucas Russell · San Rafael, US
• Ya-Chieh Lai · Mountain View, US
• Jac Paul P. Condella · Campbell, US

Key dates

• Filing date: Apr 19, 2019
• Grant date: Oct 6, 2020
• Expiry date: Apr 19, 2039

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P90/02
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems, methods, media, and other such embodiments described herein relate to critical area analysis (CAA) operations as part of electronic design automation (EDA). One embodiment involves accessing a circuit design having a first layer (which may be a composite layer), sampling the first layer, and performing an initial CAA using the sampled portions of the layer with a set of predetermined defect sizes. The initial CAA is used to automatically generate a model which can be used to accurately select input parameters (e.g., selected defect sizes) for a full analysis. A CAA characteristic is then calculated for the first layer using the input parameters. In various embodiments, different sampling percentages and criteria for selecting input parameters can be used to reduce the computing resources to compute a CAA characteristic, such as theta-bar, while limiting error to a threshold amount (e.g. less than one percent).