Method for hybrid wafer-to-wafer bonding
US10796913B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jun 6, 2017 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Jun 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83896
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for hybrid wafer-to-wafer bonding, comprising: providing two silicon wafers with Cu pattern structures, a conventional Cu BEOL process is adopted on the silicon wafers to obtain the planarized surface with copper and dielectric; removing part of the Cu on the planarized surface of the Cu pattern structures by adopting an etching process to form a certain amount of Cu recesses; depositing a layer of bonding metal on the surface of the Cu by adopting a selective deposition process; performing surface activation on the bonding metal and the dielectric by adopting a surface activation process; aligning and pressing the two silicon wafers together to obtain the dielectric bonding; and obtaining the metal bonding through the annealing process. The sufficient metal bonding can be obtained at low annealing temperature according to the present invent, thereby the risk of dielectric delaminating caused by thermal expansion mismatch is reduced, which is conducive to reduce the difficulty of process integration, save process time and improve product yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.