Semiconductor structure with partially embedded insulation region
US10796942B2 · kind B2 · utility
4Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2018 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Aug 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/657
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.