Method of fabricating novel packages for electronic components
US10797681B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2019 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Jul 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2003/023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of fabricating packaged electronic components with improved yield and at lower unit cost; the method comprising the steps of obtaining an active membrane layer on a carrier substrate, depositing a front electrode onto a front of the active membrane layer, obtaining an inner front section including at least a silicon handle or wafer, attaching an inner front end section to an outer surface of the front electrode, detaching the carrier substrate from a back surface of an active membrane on the opposite surface from the front surface on which the front electrode is deposited, patterning the active membrane layer into an array of at least one island of membrane, selectively removing the front electrode and bonding layer, selectively applying an inner passivation layer, and selectively depositing a back electrode layer on the thus exposed back surface of the active membrane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.