Patent · US Active

Receiver circuit and methods

US10797835B2 · kind B2 · utility

2Cited by

4References

8Claims

0Family size

Assignee

Telefonaktiebolaget LM Ericsson (Publ) · SE

Inventors

Yuhang Liu · Lund, SE
Joakim Axmon · Vaxholm, SE
Michael Breschel · Lund, SE
Johan HILL · Lund, SE

Key dates

Filing date	Feb 14, 2017
Grant date	Oct 6, 2020
Priority date	—
Expiry date	Jun 16, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH04L27/2689
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, and having a clock output coupled to the clock input of the ADC circuit. The clock divider circuit is configured to divide a reference clock signal coupled to the reference clock input at a reference clock frequency, to produce a clock output signal at an ADC clock frequency, at the clock output, such that the reference clock frequency is an integer multiple N of the ADC clock frequency. The clock divider circuit is further configured to select from among a plurality of selectable phases of the clock output signal, responsive to a phase selector signal applied to the phase selector input.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.