Chip substrate, manufacturing method thereof, and gene sequencing chip and method
US10801984B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 14, 2017 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Sep 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N33/48721
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A chip substrate, a manufacturing method thereof, a gene sequencing chip, and a gene sequencing method. The chip substrate includes a base substrate; first electrode, located on the base substrate in an array; an insulating layer, located at gaps between two adjacent ones of the first electrodes, and partially covering the two adjacent ones of the first electrodes to form containing spaces being in one-to-one correspondence with the first electrodes; a capacitive dielectric layer, located on a side of the first electrodes away from the base substrate, and located in the containing spaces; and second electrodes, located on a side of the capacitive dielectric layer away from the base substrate, the capacitive dielectric layer includes a first region and a second region, an orthographic projection of the second electrodes on the base substrate is overlapped with an orthographic projection of the first region on the base substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.