Clock circuitry with fault detection
US10802534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2019 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Apr 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.