Apparatus and method for fast-path memory operations
US10802723B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2013 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Mar 11, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide tightly coupled off-die memory along with an interface bus and smart buffer logic so as to efficiently perform certain frequent or repetitive operations off of a core logic. Embodiments of the present invention relieve the core logic from performing certain repetitive or frequent memory accesses and other operations so as to allow such core logic to perform other more general or varied operations. In this way, the universal interface bus, smart buffer logic, and off-die memory are specially configured to perform certain select frequent and repetitive operations while the core logic may configured to perform other operations so as to provide an improved configuration with increased computational capability and reduced power budget.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.