Systems and methods for reconfiguring dual-function cell arrays
US10802735B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2020 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Mar 5, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit die element comprises one or more field-programmable gate arrays (FPGAs) elements; a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable memory array blocks, each reconfigurable memory array block being capable of configuration and reconfiguration as a storage memory array block or as a control logic array block for controlling at least a portion of the one or more FPGA elements; and a control logic circuit functioning to configure each reconfigurable memory array block as the respective memory array block or as the respective logic array block for controlling the one or more FPGA elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.