Memory access control
US10802742B2 · kind B2 · utility
0Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Oct 5, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory array, the at least one partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to generate an active/idle signal having an active state when executing the legitimate memory access command and an idle state when executing the legitimate memory access command is complete; wherein the clock signal is disabled when the active/idle signal is in an idle state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.