Instruction memory
US10802828B1 · kind B1 · utility
39Cited by
9References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Dec 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are systems and methods for implementing a memory for an integrated circuit device. In various examples, the integrated circuit can operate the memory as a FIFO, where each address in the FIFO is directly addressable. The integrated circuit can include a first register for storing a head pointer and a second register for storing a tail pointer. When new data is written to the memory, the data cat be written starting at the tail pointer location, without the tail pointer being modified. The tail pointer can be incremented using write transactions received from external to the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.