Method, system, and device for near-memory processing with cores of a plurality of sizes
US10802883B2 · kind B2 · utility
1Cited by
1References
14Claims
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Key dates
| Filing date | Aug 21, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Dec 31, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device is configured to be in communication with one or more host cores via a first communication path. A first set of processing-in-memory (PIM) cores and a second set of PIM cores are configured to be in communication with a memory included in the device over a second communication path, wherein the first set of PIM cores have greater processing power than the second set of PIM cores, and wherein the second communication path has a greater bandwidth for data transfer than the first communication path. Code offloaded by the one or more host cores are executed in the first set of PIM cores and the second set of PIM cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.